In this lab we used both a 74LS123 dual one-shot and Verilog programming to generate digital pulses with variable widths and delays.
The goal for the first lab exercise was to use a 74LS123 dual one-shot to generate pulses with a width of 30 μs. The width of a pulse width is set using an external capacitor and resistor. The necessary values are calculated using the equation tw = kRtCext, where tw is the pulse width in time, Rt is the resistance of the external resistor, Cext is the capacitance of the external resistor, and k is a value primarily dependent upon the value of Cext that can be looked up in the datasheet of the 74LS123.
Usage of the 74LS123 required the construction of a circuit with the following layout:
where B is the trigger input to the one-shot, and Q is used for the output. A scope was attached to measure both B and Q. We decided set Cext to 0.001 μs and Rt to 68 kΩ. The expected behavior of this setup is an output pulse immediate after the rising edge of the trigger with a width of tw = 0.37 * 0.001 μs * 68 kΩ = 25.16 μs. This isn't exactly 30 μs, but we were finding that the k value of 0.37 indicated by the datasheet wasn't actually that accurate a value, and we found that if we set Cext that 0.001 μs and Rt we were reasonably successful.
We used a function generator set to TTL as a trigger for the one-shot. The output measured from the scope is shown below, with orange being the trigger input signal, and blue being the output signal:
So, as we can, the pulse does appear immediately after the rising edge of the trigger. We measured the pulse width using the cursors of the scope, and found the experimental value of 28.8 μs +/- .2 μs. Since this was a 4 % error, we decided to continue to used this setup in the second lab exercise.
The goal of the second lab exercise was to create a 30 μs pulse 1 ms after the trigger's rising edge. This can be done by attaching the inverted output of a 1 ms pulse one-shot to the trigger input of a 30 μs pulse one-shot. When the trigger is received, the inverted output of the first one-shot goes low. After 1 ms has passed, the inverted output of the first one-shot goes high again, the rising edge triggering the second one-shot, which outputs a 30 μs pulse that has been delay 1 ms by the first one-shot.
We have our setup for a 30 μs pulse one-shot from the first lab exercise, and we simply reused that setup for this lab exercise. We did need to create a 1 ms pulse one-shot, however. We calculated that the values of Cext = 10 μF and Rt = 300 Ω would yield a pulse width of tw = 0.33 * 10 μF * 300 Ω = 0.99 ms, although in practice a 300 Ω resistor didn't work as well as a 200 Ω resistor, so we actually used the values Cext = 10 μF and Rt = 200 Ω.
We attached these two one-shots together so that the circuit we constructed had the following layout:
Where C1 = 10 μF, R1 = 200 Ω, C2 = 0.001 μF, and R2 = 68 kΩ. B1 was used as the trigger input and Q2 was the output pulse, and both of these were attached to a scope.
The scope output that this circuit produced is shown below. The orange line is the trigger input and the blue line is the output from the circuit.
You can see the pulse is not immediately after the rising edge of the trigger, but delayed by a time period as we had desired. We measured the delay at 1.210 ms +/- 0.020 ms, which is close to our desired 1 ms delay. Admittedly, this is a 21 % error, and future designs would benefit from tweaking the capacitance and resistance values of the 1 ms pulse one-shot.
Zooming in the scope on just the pulse, we can more closely examine the output pulse.
We measured the pulse width at 28.8 μs +/- 0.2 μs, which is the pulse width we found from the previous exercise. This is not at all shocking since we used the same setup from the first exercise to set the width of this pulse.
Lastly, we used a Verilog program loaded into an FPGA that utilized a 50 MHz clock to generate a 30 μs pulse that is delayed from a trigger by 1 ms. The code is structured to wait for the trigger to switch from high to low, then proceed to count off clock cycles equivalent to 1 ms, switch the output from the DE2 board from low to high, count off another 30 μs worth of clock cycles, switch the output low again, and go back to waiting for a trigger. A PDF containing the actual code used is linked to below.
We took numerous pictures of the output from the DE2 board. As per the previous scope images, the orange line is the trigger and the blue line is the output. The first shows the behavior of the output with multiple triggers.
The important feature of this output is to show that the program is triggering off of a rising edge of the trigger, rather than just tirggering off of a high input.
The next image focuses on the delay of the pulse from the trigger.
The delay on the pulse was measured at 1.000 ms +/- 0.02 ms.
The next image focuses on the pulse itself, zoomed up close to measure the width of the pulse.
The width of the pulse was measured at 30 μs +/- 0.2 μs.
The output from the FPGA has 0% error that can be seen from the scope measurements. It's dead accurate, apparently. This is not too surprising, though, since all the program did was count out cycles on a reliable clock to create the delay and pulse width. Since the FPGA only implements logic, it is able to acheive far more accurate delays and widths than a one-shot chip, as the one-shot chip relies on the relatively fiddly capacitor and resistor setup.